1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM), especially to a technique to determine more surely data stored in a memory cell of MRAM.
2. Description of the Related Art
A magnetic random access memory (MRAM) collects attention as a new nonvolatile memory that it is possible a high-speed writing operation and the number of times of rewrite is large. A typical MRAM contains a memory cell array in which a plurality of memory cells are arranged in a matrix. Each memory cell contains a magnetoresistance device which is composed of a pin layer having fixed spontaneous magnetization, a free layer having spontaneous magnetization whose direction can be inverted, and a spacer layer interposed between the pin layer and the free layer.
The free layer is formed such that the direction of the spontaneous magnetization of the free layer can be set to a same direction (hereinafter, to be referred to as a parallel direction) or an opposite direction (hereinafter, to be referred to as an antiparallel direction) as or to the direction of the spontaneous magnetization of the pin layer. That is, the memory cell stores 1-bit data as a relation of the direction of the spontaneous magnetization of the free layer and the direction of the spontaneous magnetization of the pin layer. The memory cell can take two states: namely, a “parallel direction” state that the direction of the spontaneous magnetization of the free layer and the direction of the spontaneous magnetization of the pin layer are same, and an “antiparallel direction” state that the direction of the spontaneous magnetization of the free layer and the direction of the spontaneous magnetization of the pin layer are opposite to each other. The memory cell stores the 1-bit data as “1” in case of one of the parallel state and the anti-parallel state and as “0” in case of the other state.
The direction of the spontaneous magnetization in the free layer and the pin layer has an influence on the resistance of the memory cell. When the directions of the spontaneous magnetization in the pin layer and the free layer are in the parallel state, the resistance of the memory cell is a first value R, and when being the anti-parallel, the resistance of the memory cell is a second value R+ΔR. The directions of the spontaneous magnetization in the free layer and the pin layer, i.e., the data stored in the memory cell can be determined by detecting the resistance of the memory cell. The resistance of the memory cell can be detected based on either of an electric current which flows through the magnetoresistance device by applying a predetermined voltage to a magnetoresistance device or a voltage generated in the magnetoresistance device by flowing electric current through the magnetoresistance device.
As the structure of the memory cell in the magnetic random access memory, two methods are known: one method that the magnetoresistance device is connected with a bit line through an access transistor and the other method that the magnetoresistance device is directly connected with a word line and the bit line. The latter is inferior to the former in the selectivity of the memory cell but is suitable for high integration. The array composed of the memory cells in the latter is known as a cross point cell array.
Parasitic electric current (or sneak path electric current) is given as a factor that damages the reliability of determination of data stored in a memory cell of the magnetic random access memory adopting a cross point cell array. The memory cells in the cross point cell array are linked in many parallel routes. The sneak path electric current flows through the memory cells as a read object through the parallel routes without passing it. The sneak path electric current hinders the correct detection of the resistance of the memory cell when the data stored in the memory cell is determined.
A magnetic random access memory is disclosed in Japanese Laid Open Patent Application (JP-P 2002-8369), in which the resistance of a memory cell in the cross point cell array is detected in a high reliability while restraining an influence of the sneak path electric current. FIG. 1 is a schematic diagram showing the conventional magnetic random access memory. The magnetic random access memory contains a resistive cross point array 110 composed of a plurality of memory cells 112. The resistive cross point array 110 contains a plurality of word lines 114 extending in a row direction and a plurality of bit lines 116 extending into a column direction. Each of the memory cells 112 is located on the intersection of the word line 114 and the bit line 116. The word line 114 is connected with a row decoder circuit 118 which selects one of the plurality of word lines 114. The bit line 116 is connected with a detection circuit 120. The detection circuit 120 is composed of direction control circuits 122, each of which selects one of the plurality of bit lines 116, a sense amplifier 124 for each direction control circuit 122, a data register 130 for each sense amplifier 124 and an input/output pad 132 for each data register 130.
A read operation of the magnetic random access memory is carried out as follows. That is, one word line 114 is selected by the row decoder circuit 118 and one bit line 116 is selected by the direction control circuit 122. The memory cell 112 located on the intersection of the selected word line 114 and the selected bit line 116 is selected.
FIG. 2 shows an equivalent circuit of the resistive cross point array 110 at the time of the data read. The selected memory cell is shown by a first resistor 112a and the memory cells which are not selected are expressed by the second, third, and fourth resistors 112b, 112c and 112d. The second resistor 112b represents a not-selected memory cell along the selected bit line, the third resistor 112c represents a not-selected memory cell along the selected word line and the fourth resistor 112d represents not-selected other memory cells.
An operation potential Vs is applied to the selected bit line, and a ground potential is applied to the selected word line. Thus, a detection electric current Is flows through the first resistor 112a. The operation potential Vb which is the same as the operation potential Vs is applied to the bit line which is not selected, to restrain the influence of sneak path electric current. The sneak electric currents S1 and S3 which respectively flow through the second resistor 112b and the fourth resistor 112d are blocked off by the application of the operation potential Vb. Moreover, the sneak path electric current S2 which flows through the third resistor 112c is led to the ground potential. Therefore, it does not interfere with the detection electric current Is. In this way, the detection electric current Is can be detected in a high reliability.
Alternatively, the same operation potential Vb as the operation potential Vs is applied to the word line which is not selected, as shown in FIG. 3. Thus, the sneak path electric current S1 is blocked off so as not to flow through the second resistor 112b. The sneak path electric current S2 which flows through the third resistor 112c and the sneak path electric current S3 which flows through the fourth resistor 112d are led to the ground potential. Therefore, they do not interfere with the detection electric current Is. In this way, the detection electric current Is can be detected in a high reliability.
By applying the operation potential Vb which is the same as the operation potential Vs to the bit line which is not selected, or by applying the operation potential Vb which is the same as the operation potential Vs to the word line which is not selected, the detection electric current Is can be detected in a precision. Therefore, the data stored in the selected memory cell can be detected in a high reliability.
In the above-mentioned magnetic random access memory, it is important that the operation voltage Vb which is applied to the word line (or the bit line) which is not selected and the operation voltage Vs which is applied to the selected bit line are coincident with each other in a high precision. A little difference between the operation voltage Vb and the operation voltage Vs conspicuously increases the influence of the sneak path electric currents S1 to S3 on the detection electric current Is. Especially, when the memory cell has a short-circuit in a part because of a problem on a manufacturing process, the little difference between the operation voltage Vb and the operation voltage Vs generates a large sneak path electric current.
However, it is difficult in practice to coincide the operation voltage Vb with the operation voltage Vs totally. The difficulty to coincide the operation voltage Vb and the operation voltage Vs totally decreases the effect of the restraint of the influence of the sneak path electric current.
It is demanded that the data stored in the memory cell of the magnetic random access memory can be read in a high reliability, excluding the influence of the sneak path electric current.
In conjunction with the above description, a circuit to confirm a write state of a flash memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-29494). The circuit of this conventional example is applied to an EEPROM array which has a plurality of memory cells. The memory cell is formed on a silicon substrate to have a floating gate. The floating gates of the memory cells are connected with one of a plurality of word lines. The circuit to confirm a write state of the memory cell contains a first circuit which generates a first reference electric current. The first circuit is connected to the word line, and has a first threshold potential which is set to a first fixed level. A memory cell electric current is generated in response to a gate potential applied to the word line. Also, when the gate potential is larger than the first threshold potential, the first reference current is generated. A detection circuit is connected with the memory cell to respond the first reference electric current. The detection circuit confirms a program state when the memory cell electric current is larger than the first reference the electric current.
Also, a non-volatile semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-342598). The non-volatile semiconductor memory device of this conventional example contains a memory cell array in which memory cells of non-volatile transistors are arranged in a matrix, and a dummy cell which has a transistor structure. A read potential generating circuit applies a predetermined potential to a selected one of the memory cells such that a read potential corresponding to the data stored in the selected memory cell is generated based on the electric current flowing through the selected memory cell. A reference potential generating circuit applies a predetermined potential to the dummy cell such that a reference potential is generated based on the electric current flowing through the dummy cell. A reference potential falling circuit falls the reference potential for a first predetermined time after change from a standby state into an operating state. An amplification circuit compares the read potential and the reference potential after a second predetermined time after the change from a standby state into the operating state and amplifies and output an output according to the comparison result.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-39858). In the semiconductor memory device of this conventional example, a sub cell block is composed of a single memory cell which is provided at intersection of a word line and a bit line and stores data through a resistance change. Alternatively, the sub cell block is composed of a plurality of memory cells which are connected in series in a direction of the bit line. A cell block is composed of a plurality of sub cell blocks which are connected in series in the direction of the bit line. A memory cell array is composed of a plurality of cell blocks which are provided in a direction of the word line. A circuit supplies an electric current to the cell block in the bit line direction. A read circuit reads data from nodes at both ends of the sub cell block which contains the memory cell of the sub cell block which is selected by the word line.
Also, a magnetic random access memory device is disclosed in Japanese Laid Open Patent Application (JP-P2001-273756A). The magnetic random access memory device is composed of an array which contains a plurality of columns of memory cells and at least one column of reference cells, a plurality of bit lines which extend to connect memory cells from one memory cell of each column to the reference cell, and a read circuit which detects a resistance state of the selected memory cell in the array. The read circuit contains a plurality of steering circuit which have inputs connected to the plurality of bit lines, respectively. A plurality of differential amplifiers are provided for the steering circuits and each of the plurality of differential amplifiers has a sense node and a reference node. Each of a plurality of first electric current mode preamplifiers is connected between the output of a corresponding one of the steering circuits and the sense node of corresponding one of the differential amplifiers. A plurality of second electric current mode preamplifiers are connected between the standard nodes of the differential amplifiers and the bit lines, respectively.
Also, a magnetic random access memory device is disclosed in Japanese Laid Open Patent Application (JP-P2000-315383A). The magnetic random access memory device of this conventional example is composed of a row decoder which decodes a part of an address, a column decoder which decodes the remaining part of the address, a plurality of pairs of sense lines, each pair being connected with a decoding terminal of the row decoder, a plurality of word lines connected with decoding terminals of the column decoder, and a plurality of cell pairs. Both of the sense lines of the pair are provided adjacent to each other and the cell pair is composed of a memory cell and a reference cell which are provided adjacent to each other. The memory cell and the reference cell have magnetoresistance elements, respectively. The pairs of the sense lines and the plurality of word lines intersect in a matrix. In the intersection, the memory cell is connected with one of the sense lines and the word line and the reference cell is connected the other of the sense line and the word line.